The present invention is generally drawn to and analog-to-digital converters (ADCs) that employ successive approximation registers (SARs).
A SAR is a type of ADC that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion. An example conventional ADC will now be described with reference to FIGS. 1A-C.
FIGS. 1A-1C illustrate a conventional ADC 100. FIG. 1A illustrates ADC 100 estimating an input voltage using a most significant bit, whereas the FIG. 1B illustrates ADC 100 estimating the input voltage using the next most significant bit, and whereas FIG. 1C illustrates ADC 100 estimating the input voltage using the least significant bit.
As shown in FIG. 1A, ADC 100 includes a sample and hold (S/H) component 102, a comparator 104, a SAR 106 and a digital-to-analog converter (DAC).
S/H component 102 is arranged to receive on analog input voltage, Vin, from an input line 110 and is arranged to output a sampled and held analog voltage, Vx, onto an output line 112. S/H component 102 samples and holds Vin until it is need.
Comparator 104 is arranged to receive Vx from output line 112 at a first input and to receive and output voltage, Vout, from DAC 108 from an output line 114 at a second input. Comparator 104 is also arranged to output a compared signal, based on a comparison of Vx and Vout, to a line 116.
SAR 106 is arranged to receive the compared signal from line 116 and to receive a clock signal from a clock line 118. SAR 106 is arranged to output SAR output values to output lines 120, 122 and 124 to ultimately provide a digital representation of an approximation of Vin.
DAC 108 is arranged to receive a reference voltage, Vref, via a reference line 111. DAC 108 provides Vout based on Vref and the SAR output values from SAR 106.
In operation, conventional ADC 100 provides a digital output corresponding to an analog input. For purposes of discussion, let Vin be 3.7 V. Initially, SAR 106 starts with the most significant bit and asks “is it greater than 4 V?” A digital value of “1” is output to output line 120, a digital value of “0” is output to output line 122 and a digital value of “0” is output to output line 124, DAC 108. In this example, let Vref be 1 V, such that Vout is in 1 V increments associated with the digital value provided by SAR 106. Accordingly, DAC 108 outputs Vout as an analog value of 4 V to comparator 104 via output line 114.
Comparator 104 compares the 4 V from DAC 108 and the 3.7 V provided by S/H component 102, and indicates that Vin “is not greater than 4 V,” thus outputting a digital “0” to SAR 106.
As shown in FIG. 1B, SAR 106 then resets the most significant bit to “0” and sets the next bit to a digital “1,” and asks “is it greater than 2 V?” A digital value of “0” is output to output line 120, a digital value of “1” is output to output line 122 and a digital value of “0” is output to output line 124, DAC 108.
DAC 108 then outputs Vout as an analog value of 2 V to comparator 104 via output line 114.
Comparator 104 compares the 2 V from DAC 108 and the 3.7 V provided by S/H component 102, and indicates that Vin “is greater than 4 V,” thus outputting a digital “1” to SAR 106.
As shown in FIG. 1C, SAR 106 then sets the next bit to a digital “1,” and asks “is it greater than 3 V?” A digital value of “0” is output to output line 120, a digital value of “1” is output to output line 122 and a digital value of “1” is output to output line 124, DAC 108.
DAC 108 then outputs Vout as an analog value of 3 V to comparator 104 via output line 114.
Comparator 104 compares the 3 V from DAC 108 and the 3.7 V provided by S/H component 102, and indicates that Vin “is greater than 3 V,” thus outputting a digital “1” to SAR 106.
At this point, it is determined that Vin is less than 4 V but greater than 3 V. As such SAR 106 has gone through all bits and reached an end to the conversion, so the digital representation of the analog Vin is output as “001” on output lines 120, 122 and 124.
In some applications, analog voltages on a plurality of input lines, or multichannel inputs, may need to be converted to digital signals. Conventionally, multichannel ADCs may be used for such conversions. Some example conventional multichannel ADCs will now be described with reference to FIGS. 2-3.
In one type of conventional multichannel ADC, multiple SAR ADCs are used to simultaneously sample and convert analog voltages, in parallel. These converted signals are then provided to a central processing portion for serial output. This will be described with reference to FIG. 2.
FIG. 2 illustrates an example conventional multichannel ADC 200.
As shown in the figure, conventional multichannel ADC 200 includes a SAR ADC 202, a SAR ADC 204, a SAR ADC 206 a SAR ADC 208 and a controller component 210.
SAR ADC 202 is arranged to receive an analog input voltage, Vin1, from an input line 212 and is arranged to output a digital output voltage, Vo1, onto an output line 214. SAR ADC 204 is arranged to receive an analog input voltage, Vin2, from an input line 216 and is arranged to output a digital output voltage, Vo2, onto an output line 218. SAR ADC 206 is arranged to receive an analog input voltage, Vin3, from an input line 220 and is arranged to output a digital output voltage, Vo3, onto an output line 222. SAR ADC 208 is arranged to receive an analog input voltage, Vin4, from an input line 224 and is arranged to output a digital output voltage, Vo4, onto an output line 226.
Controller component 210 is arranged to receive Vo1 from output line 214, to receive Vo2 from output line 218, to receive Vo3 from output line 222, to receive Vo4 from output line 226 and to output a digital output voltage, Vout, onto an output line 228.
In operation, conventional multichannel ADC 200 receives Vin1, Vin2, Vin3 and Vin4 in parallel. Each analog input voltage is converted to a respective digital representation in parallel. Controller 210 then outputs digital voltages serially.
A problem multichannel ADC 200 is that the plural SAR ADC require much power and use a large amount of circuit real estate. Further, there is a higher channel to channel mismatch due to the presence of separate ADCs on each channel
In another type of conventional multichannel ADC, multiple S/H components are used to simultaneously sample analog voltages. These sampled signals are then provided to a PGA before being serially converted. This will be described with reference to FIG. 3.
FIG. 3 illustrates another example conventional multichannel ADC 300.
As shown in the figure, ADC 300 includes ADC 100 of FIG. 1 in addition to an S/H component 302, an S/H component 304, an S/H component 306, an S/H component 308 and a programmable gain amplifier (PGA) or an active sample and hold amplifier (SHA) 310.
S/H component 302 is arranged to receive an analog input voltage, Vin1, from an input line 312 and is arranged to output a sampled and held analog voltage, Vs1, onto an output line 314. S/H component 304 is arranged to receive an analog input voltage, Vin2, from an input line 316 and is arranged to output a sampled and held analog voltage, Vs2, onto an output line 318. S/H component 306 is arranged to receive an analog input voltage, Vin3, from an input line 320 and is arranged to output a sampled and held analog voltage, Vs3, onto an output line 322. S/H component 308 is arranged to receive an analog input voltage, Vin4, from an input line 324 and is arranged to output a sampled and held analog voltage, Vs4, onto an output line 326.
PGA 310 is arranged to receive Vin1 from output line 112, Vin2 from output line 318, Vin3 from output line 322 and Vin4 from output line 322. PGA 310 is additionally arranged to output an analog voltage as Vin onto line 110.
In operation, conventional multichannel ADC 300 samples and holds Vin1, Vin2, Vin3 and Vin4 in parallel with S/H component 302, S/H component 304, S/H component 306 and S/H component 308. To ensure that the sampled voltage is accurately converted, the entire voltage stored in any one of S/H components 302, 304, 306 and 308 must be transferred to S/H component 102. To ensure that the sampled voltage is entirely transferred, PGA 310 is provided.
Each analog input voltage is provided to PGA 310, which outputs amplified versions of the analog input voltages serially. Comparator 104, SAR 106 and DAC 108 then serially converts each amplified signal to digital representation in a manner similar to that discussed above with reference to FIGS. 1A-C.
A problem multichannel ADC 300 is that PGA or SHA requires much power and use a large amount of circuit real estate. Being active circuits, both the PGA and the SHA introduce more noise and other non-idealities of their own into the circuit, which leads to higher error in the precision circuit.
What is needed is a passive multi-channel ADC that uses a single SAR ADC that does not require multiple DACs (or ADC) or does not require any PGA or any SHA.